![]() Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), ramped up mass production in May of 2017. Samsung demonstrated their 128 Megabit SRAM wafer from their 10nm FinFET process. Because of the ever shrinking geometries the wires get smaller each node. ![]() This is the first time cobalt is used in a high volume production node. The process can support multiple threshold voltages, and features 12-metal interconnect layers with the bottom two made of cobalt. Intel's 10nm process is roughly 1.7x the raw logic density of the next densest 10nm process, albeit due to aggressive pattering techniques they also have the most complex process available to date. Intel expect their "10nm+" process to surpass that. Intel's initial 10 nm process has up to 60% lower power and 25% better performance than their initial 14 nm but will actually have lower performance than their "14nm++" process. Intel detailed Hyper-Scaling, a marketing term for a suite of techniques used to scale a transistor, SAQP, a single dummy gate and contact over active gate (COAG). Although both TSMC and Samsung's 10nm processes are slightly denser than Intel's 14nm in raw logic density, they are far closer to Intel's 14nm than they are to Intel's 10nm (e.g., Samsung's metal pitch just 1 nanometer shorter than Intel's 14nm).Īnnounced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is Intel's first high-volume manufacturing process to employ Self-Aligned Quad Patterning (SAQP) with production starting in the second half of 2017. Due to the small feature sizes, for the critical dimensions, quad and triple patterning were introduced for the first time in high-volume manufacturing.Īt the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: Intel, Samsung, and TSMC.ĭue to marketing names, geometries vary greatly between leading manufacturers. Those nodes typically have a gate pitch in range of 50-60s nm and a minimum metal pitch in the range of 30-40s nm. Unfortunately each company uses a different structure as a reference, so you can't compare the nm number between companies.First introduced between 2017-2019, the 10 nm process technology is characterized by its use of FinFET transistors with a 30-40s nm fin pitches. Solandri said:The nm refers to the size of certain structures used to make transistors. So if you figure a 1 nm process results in about 25% the linear density of their 5 nm process, then you get transistors about 140 x 140 atoms across. If you compare transistor density to process, the relationship is close to (but slightly less than) the square. Or 570x570 atoms per transistor if they were square (less probably after accounting for dead space between transistors). Or about 325,000 atoms (surface area) per transistor. So 1 mm^2 = 7.5 million x 7.5 million silicon atoms. TSMC 3nm is supposed to be 70% higher than their 5nm, which would be about 290 MT/mm^2.From what I gather, a silicon atom is about 0.132 nm across. Intel 7nm (if it ever gets here) is estimated to be at about 225-250 MT / mm^2, Intel 10nm is about equal to TSMC 7nm (both around 100-110 MT / mm^2). TSMC 12nm is about 29 million transistors / mm^2 Unfortunately each company uses a different structure as a reference, so you can't compare the nm number between companies. The transistors are actually much bigger.The nm refers to the size of certain structures used to make transistors. Techrabbit2015 said:For all of you excited about how many atoms wide these are, this isn't how these companies are designating "1nm" or even "5nm" at this stage.
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